FROM THE EDITOR
This week we delve into the realm of high-level
design with two articles. First, we take a look at languages and
methodologies beyond the current RTL/HDL standard in "Leading
Languages". We have looked into our crystal ball and seen the
future of design (again) and here is our best updated guess as to
what that future holds.
Next we have a contributed
article from Poseidon Systems on methodologies and tools for
accelerating processor-based systems with effective
hardware/software partitioning. Poseidon is a new entrant into the
race for the perfect partitioning environment, and this article
explains the new company's design philosophy and initial
offering.
Thanks for reading! If
there's anything we can do to make our publications more useful to
you, please let us know at: comments@fpgajournal.com
Kevin Morris –
Editor FPGA and Programmable Logic
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Leading Languages
Is There a Future Beyond
RTL?
I still check occasionally on gizmodo.com or engadget.com,
but I've pretty much given up hope. It's now 2005. Throughout my
childhood, I was convinced that by this year I'd be flying around in my
jetpack, or at least driving my flying car. My personal robot is a bit
closer to reality, but still not in the cards for the foreseeable future,
unless I just want my floors vacuumed. The one-MIPS supercomputer I had
visualized in my basement, however, complete with dumb terminal and tape
drives, has far exceeded expectations.
Our view of the future is always distorted, even if we
have pretty solid trends to extrapolate. Either an anticipated key
technology fails to mature, or an unexpected breakthrough occurs pushing a
dark horse into the lead. In 1995, I was certain that RTL design would be
dead by now, and that everyone would be designing digital hardware in
behavioral VHDL. The enabling technology I was expecting was behavioral
synthesis. Like those personal jetpacks, a few first-generation behavioral
synthesis efforts got off the ground, but none ever proved sturdy or
reliable enough that you'd want to strap-in your career and light the
fuse. Instead, RTL design has clung to life in the mainstream, bolstered
by increasingly elaborate scaffolding that strains under the weight of
bloated semantics with today's monstrous designs. [more]
Accelerating Processor-based Systems
by Farzad Zarrinfar, Bill
Salefski, and Stephen Simon, Poseidon Design Systems
Designing an efficient processor-based system
architecture with overall system performance optimized for a specific
application is not trivial, requiring skills and technology similar to
those employed by supercomputer designers. Accomplishing this feat
requires new tools and methodologies to augment the EDA flow for both
traditional ASIC design and the new class of programmable SoCs, e.g.,
FPGAs. Architectures and performance must be verified early in the design
cycle; the designer cannot wait until RTL development to discover their
architecture does not support their system requirements.
Problems to Solve Current processor
tools have not kept up with the challenges of the new high-performance
systems. Designers need tools to explore and exploit performance, power,
and cost opportunities in their processor-based designs. [more]
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